This relates generally to electronic circuitry, and more particularly to a method and circuitry for sensing and controlling a current.
FIG. 1 (prior art) is a schematic electrical circuit diagram of a conventional step down converter, indicated generally at 100. For sensing current of a high-side power n-channel field-effect transistor (“NFET”) MN1, an NFET MNSNS is connected in parallel with MN1, so that both of them share common drain and gate connections. The drains of MN1 and MNSNS are connected to an input voltage node (having a voltage VIN). The gates of MN1 and MNSNS are connected to an output of a driver 102, which: (a) receives a voltage signal VGD from control circuitry 104; and (b) drives VGD through such output to those gates.
A source of MNSNS is connected to a node A, which is further connected to a first input (“+”) of an amplifier 106. A source of MN1 is connected to a node B (having a voltage VSW), which is further connected to a second input (“−”) of the amplifier 106. An output of the amplifier 106 is connected to a gate of an NFET MNA.
A source of MNA is connected to a ground, and a drain of MNA is connected to the node A as feedback. Accordingly, while the amplifier 106 is active, MNA and the amplifier 106 operate together for holding the node A's voltage relatively near (e.g., slightly above) the node B's voltage. In that manner, MNSNS senses a current that flows through MN1, while MNA senses a current that flows through MNSNS. An NFET MNB mirrors a current that flows through MNA.
While MN1 and MNSNS are turned on, they conduct respective amounts of current, according to a channel width ratio between MN1 and MNSNS. In one example, such channel width ratio is relatively large, so that MN1 conducts current on an order of amps, while MNSNS, MNA and MNB conduct current on an order of microamps.
As shown in FIG. 1, the node B is coupled through a diode 108 (having a voltage drop −VD) to the ground. Also, the node B is coupled through an inductor L (having a variable current IL) to a node C (having a voltage VOUT). The node C is coupled through a capacitor C to the ground. Further, the node C is coupled through a load 110 (having a current ILOAD) to the ground.
The control circuitry 104 is connected to a drain of MNB. In response to a current ISENSE that flows through MNB, and in response to VOUT, the control circuitry 104 suitably adjusts VGD as feedback to control (e.g., selectively enhance, and selectively limit) IL by alternately switching MN1's gate on and off.
During each switching cycle, VSW swings from −VD to near VIN. In one example, the amplifier 106: (a) is inactive while VSW≈−VD, which is outside an input range of the amplifier 106; and (b) becomes active when VSW rises to near VIN. Nevertheless, while VSW rises, ISENSE incorrectly overshoots, because MN1's initial VDS≈VIN+VD. Accordingly, the control circuitry 104 ignores ISENSE at the beginning (blanking time) of each switching cycle, which limits a minimum duty cycle of the circuitry 100 and its maximum switching frequency.
Also, through the node B, the second input (“−”) of the amplifier 106 is directly connected to an external high-voltage switching node, which exposes the second input (“−”) to the switching node's parasitics and electrostatic discharge (“ESD”). Accordingly, to protect the second input (“−”) against high-voltage ESD, the amplifier 106 includes additional circuitry for such protection, even if MN1 is self-protecting.